1. Field of the Invention
The invention relates to memory control systems used in computer systems, and more particularly to systems utilizing cache memory and paged main memory.
2. Description of the Prior Art
Personal computer systems are becoming increasingly prevalent and increasingly more powerful. Early personal computer systems, while a great advance over manual systems, were relatively simple and had limited capabilities. Personal computers took a step forward in capabilities when International Business Machines Corporation (IBM) introduced the original IBM PC. That computer was based on the 8088 microprocessor developed by Intel Corporation. The IBM PC was more powerful than earlier personal computers and new functions and capabilities for the IBM PC were rapidly developed. The components available for use in personal computers advanced significantly over this period and soon the design of the IBM PC was too limited, especially after the introduction by Intel Corporation of the 80286 microprocessor.
Personal computer users were demanding the available improvements and IBM introduced the IBM PC/AT, which utilized the 80286 microprocessor and many of the advanced devices which had been developed since the IBM PC was introduced. This machine satisfied users for a period of time, but again the capabilities of available components for use in personal computers increased and the demand for increased performance persisted.
The operating system utilized in IBM compatible computers was developed for use with the IBM PC and its incorporated 8088 microprocessor. The 8088 has 20 address pins and so only 1 Mbyte of memory is directly addressable. This was satisfactory in the early stages, but the availability of the 80286 and its 24 address lines and the need for programs accessing more than the available 640 kbytes of random access memory under the operating system rendered the operating system a limitation on personal computer performance. Various formats were developed to resolve this operating system imitation. One such format was the LIM expanded memory specification (LIM EMS), which used a window available in the memory space accessible under the operating system to access mode memory. The location of the window over the physically available memory was controlled by information passed through the input/output space. Thus, significantly greater amounts of memory could be accessed without a revision of the operating system and with only the inclusion of window control programming in the application program utilizing the additional memory.
To abate the user demand, Intel Corp. introduced the 80386 microprocessor. The increased speed of this unit helped to temporarily resolve the performance demand problem, but soon users still demanded more performance. One technique used in advanced or large computer architectures to increase performance was the use of cache memory. Cache memory is very fast memory which allows the microprocessor to operate at its full potential when operating out of this fast memory, unlike when operating out of main memory, where cost considerations limit the speed of the memory utilized. However, because of the relatively high cost of this cache memory, only portions of the information in the main memory are kept in the cache memory. This use of only portions requires that the cache memory system keep track of which portions of the main memory are duplicated in the cache memory.
This requirement to keep track of which portions of the main memory are located in the cache memory, called coherency, is difficult when utilizing memories which implement the LIM EMS or other paged memory techniques, wherein different physical memory locations can be addressed at the same logical address. For example, if the LIM EMS window is pointing to a first physical memory location and the cache memory saves the data at this location, the cache memory system thinks it has stored the data at a given location in the logical address space of the window. The window is then moved to a different physical portion of the memory, but the window logical address does not change. Thus the information present at the location preserved by the cache memory system is not what is currently present at that location. This creates a cache coherency problem and the specific location in the cache memory must be cleared or nullified.
One device commonly utilized in present personal computer systems to control the cache memory is the Intel Corporation 82385 cache controller. The 82385 does not allow individual cache memory locations to be cleared under certain circumstances, such as those described above. To this end, a cache flush operation must be performed which clears all entries in the cache memory system. In the past, to avoid the difficulties of determining when a cache flush was necessary, the designs have required that the applications programs or drivers used with LIM or paged memory systems insure that coherency problems did not develop. This was a burden on the programs and reduced their performance.
With the user demand for higher performance noted, a number of sources considered the architecture of the AT insufficient to properly utilize the full capabilities of then available components and of components which would clearly be available in the relatively near future. Certain operations, such as multiple bus master operations, were exceedingly difficult to perform and only marginal performance improvements could be obtained. To this end a new architecture or interface standard was developed.
IBM introduced a new line of personal computers, called the Personal System/2 or PS/2. A number of the machines available in the PS/2 family utilized the new interface standard, referred to as the Micro channel Architecture or MCA, to allow the advanced, desired capabilities to be provided at a high performance level. In addition to the conventional address, data and control signals necessary for operation, the MCA provides a card selected feedback signal or CD.sub.-- SFDBK*(n), where the (n) indicates that a separate signal exists for each circuit board location. This signal provides feedback to the computer system to indicate which circuit board has responded to the operation presented on the system signal bus. For detailed information on the MCA, please refer to the IBM Personal System/2 Model 80 Technical Reference Manual, having a copyright date of 1987 and a product number of 84X1508.
One of the features provided by the MCA was the ability to initialize circuit board parameters entirely by program control, without the need to set any jumpers or switches. This feature was called Programmable Option Select (POS) and utilized certain defined input/output (I/O) space locations or ports to control which circuit boards or adaptors were being configured and where configuration information was to be located. A circuit board was configured by first selecting which circuit board location was to be addressed and placing the circuit board in setup or configuration mode. The configuration information was then loaded and setup mode exited.
Configuration information which could be transferred depended on the function of the particular circuit board being configured. For example, if a memory board was being configured, the information would include the memory space address locations to which the memory board would respond.
This programmable configuration capability is desirable, but also creates a potential cache coherency problem, similar to those discussed previously. The cache memory system could remember a given logical address and the computer system could reconfigure its resources, with another element ending up at the given logical address. Additionally, reconfiguration is a high level function which indicates major changes could be occurring in the computer system, with many possible cache coherency ramifications.